2025大赛优秀作品 | 基于Ansys的XDFOI晶圆级封装工艺的翘曲模拟与实验验证

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作品名称：基于Ansys的XDFOI晶圆级封装工艺的翘曲模拟与实验验证

Warpage Simulation and Experimental Validation of The X-Dimension Fan-Out Integration-Bridge Wafer Level Packaging Process

作者： 程健 | JCET专家工程师

关键词：advanced package, bridge die chip, wafer level packaging, warpage simulation, element birth and death method, viscoelastic material model

作者说

Simulating chip packaging mechanics with Ansys has deepened my understanding of Thermo-Mechanical coupling effects. The software's ability to model solder joint fatigue, complicate process warpage of 2.5D wafer, drop and vibration test etc. that align with experimental data well. I really appreciate Ansys provides user-friendly tools to enable complicated simulations in the field of chip packaging. However, challenges persist in defining realistic material properties for underfill resins and encapsulants. Convergence issues often arise when simulating delamination at heterogeneous interfaces, requiring adaptive meshing techniques. These experiences highlight that while Ansys provides powerful tools, domain-specific material knowledge remains essential for meaningful results. We hope to work together with Ansys to achieve shared progress and growth in simulation fields.

In this paper, the full wafer level packaging process flow of a novel large x-dimension fan-out integration bridge (XDFOITM) die chip is introduced. The warpage values of its full manufacturing process are investigated by finite element analysis and validated by manufacturing test data. To simulate the full packaging process flow warpage and consider the influence of residual strain and stress at each step, the element birth and death technique is introduced to the finite element analysis (FEA) model with an equivalent structure and material parameters by theoretical method to equivalently simplify the structure of redistribution layer (RDL). The reference temperature of RDL is recalculated too. The viscoelastic material model of Epoxy Molding Compound (EMC) is used to simulate the curing process. This full process warpage simulation results at several packaging steps are validated by warpage test data which showing the accuracy between simulation and test data is above 75%. Furthermore, this paper discusses the key measures to reduce the wafer level packaging process warpage values from various aspects such as material CTEs matching, elastic modulus of glass carrier, etc. The method introduced in this paper can be used to predict and reduce the wafer level packaging process warpage of an advanced packaging structure.

挑战/需求

JCET XDFOITM Solution: The X-Dimension Fan-Out Integration Bridge, 2.5D WLP with complicated typical 12 processes as shown in Figure 1.

Warpage induced issues during WLP process: Die crack; Interface delamination between PI and EMC, ELK and passivation, etc.; Processing failure due to excessive warpage over the equipment tolerance.

FEA is used to investigate warpage risk for full WLP process with challenges: A large model of complicated wafer structure; The viscoelastic behavior of polymer materials, EMC; The effect of sequential residual stress and strain on WLP warpages during full packaging process, etc.

使用工具

Equivalent calculation by energy approach and force, strain equivalent method to simplify the wafer mic-structure as shown in Figure 2.

Ansys Mechanical with element birth and death method to simulate the full packaging process as shown in Figure 3.

最终成果

• The full WLP processes of XDFOITM are introduced
• Modeling approach with element birth and death method and structures equivalent are used to investigate the warpages of the XDFOITM
• Numerical modeling warpages can be correlated well with test data
• The effects of key parameters, ETC and Young’s Modulus on WLP wafer during full process are also studied in this paper
• Reducing CTE of EMC would significantly reduce the warpages in glass detached process
• Increasing the CTE of UF would reduce the WLP wafer warpage
• Decreasing the CTE and Young’s modulus of glass would significantly decrease the warpage in stage 2, flip chip die, UF and EMC2 curing processes

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